The present invention relates to an integrated memory having a plurality of memory cell arrays which in each case have word lines for the selection of memory cells and bit lines for reading out or writing data signals of the memory cells.
Integrated memories usually have one or more memory cells connected to the bit lines and word lines. In this case, the memory cells are disposed at crossover points between the bit lines and word lines. The memory cells are in each case connected to one of the word lines. For the selection of the memory cells, in the case of a dynamic random access memory (DRAM), for example, selection, transistors of memory cells are turned on by an activated word line, as a result of which a data signal can subsequently be read out from or written to a corresponding selected memory cell. For this purpose, the selected memory cell is connected via the selection transistor to one of the bit lines, via which the corresponding data signal is read out or written in.
In the case of a memory cell access, usually a plurality of memory cells are read from or written to within an access cycle. By way of example, all of the memory cells along an activated word line can be read from or written to. Such a memory cell access is generally referred to as a so-called burst and the number of selected memory cells or the number of read or write steps to be performed within an access cycle is referred to as the burst length.
The burst length is usually programmed in a so-called mode register. During an access cycle, a respective decoder that is assigned to a memory cell array is addressed for the selection of a word line and a number of bit lines, depending on the burst length. In this case, the decoder can carry out the actions of activation, reading or writing and precharging, or select the relevant word line and relevant bit lines therefor.
In order to achieve very high frequencies, for example greater than 200 megahertz, at high data rates, the column address can be altered, for example, by a counter in the event of activation of a word line during a burst. However, the performance of memory accesses using this principle is limited, especially as an additional counter, a so-called column counter, is necessary which, in the case of an active word line and during a burst, can change over the column address from a first to a second address.
It is accordingly an object of the invention to provide an integrated memory having a plurality of memory cell arrays that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which enables high data rates even at very high frequencies with a low outlay.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory. The memory contains a plurality of memory cell arrays having memory cells, word lines for selecting the memory cells, and bit lines for reading out or writing in data signals from/to the memory cells. Decoders, including word line decoders and a bit line decoder, are connected to the memory cell arrays for selecting the bit lines and the word lines. A control circuit has an input side and is connected to the decoders. The control circuit addresses the word lines and the bit lines, and if one of a read command and a write command is present on the input side of the control circuit, at least two of the word lines can be activated simultaneously. A multiplexer is provided and has an input side coupled to the bit line decoder for addressing the bit lines. The multiplexer is configured such that in a burst mode read access, in each clock period, a datum assigned to addressed memory cells is output until a burst mode operation advances by a predetermined burst length.
The control circuit may be a mode register, for example.
In this case, in the integrated memory described, a continuous data stream is to be understood to be that, by use of the multiplexer, in a burst mode operation, in each clock period, a datum assigned to the addressed memory cells is output until the burst mode operation advances by a predetermined burst length.
In this case, the burst length can be predetermined by the definition of the simultaneously activated word lines by the control circuit.
As a result of simultaneous activation of a plurality of word lines, a corresponding multiple of data is available at a data output of the integrated memory, which can be coupled to the bit line decoder of the memory. By way of example, if two word lines are activated, twice as many crossover points between activated word lines and activated bit lines are produced, with the result that overall twice as many data bits can be read out, in other words the burst length is doubled compared with conventionally one activated word line.
Correspondingly, if four word lines are selected simultaneously, four times the volume of data, that is to say four times the burst length, is achieved. In a read access with more activated word lines, more data are made available from the semiconductor memory and are then combined by the multiplexer to form a continuous data stream.
Consequently, in the case of the principle described, the burst length is determined by the number of word lines simultaneously selected or activated by the control circuit. Accordingly, a variable burst length can be attained with the present principle.
As already explained in the introduction, burst length is to be understood to be the number of selected memory cells or the number of read or write steps to be performed within an access cycle.
According to the invention, a write operation is also possible by analogy with the read operation described, during which write operation a continuous data stream is correspondingly broken down by the multiplexer, in a demultiplexing operation, into data to be written to the different memory cells assigned to the respective word lines.
Preferably, each memory cell array may be assigned a dedicated row decoder for the addressing of the word lines of the assigned memory cell array.
As an alternative or in addition, a common column decoder may be provided which is assigned to a plurality of memory cell arrays.
The special feature in the present invention is that there is no changeover (toggling) between different columns during a burst, and, accordingly, a column address counter, a so-called column counter, required for this can be obviated.
Overall, the principle described yields, at very high frequencies of even greater than 200 megahertz, a high data rate with a variable burst length. In this case, the burst length may be proportional to the number of activated word lines and may be, for example, two, four or eight.
The integrated memory described also has advantageous properties with regard to the power loss and thus with regard to the evolution of heat, since although activating a doubled number of word lines in accordance with the proposed principle requires a doubled current, the simultaneous doubling of the burst length on account of the doubled volume of data results, however, that double the time is available, so that overall the power remains the same.
Since the plurality of word lines which can be activated simultaneously must be accessible independently of one another in the integrated memory, they may be disposed in different memory cell arrays, each having a dedicated driver stage (sense amp block), and be addressable independently of one another, for example by independent row decoders.
In one advantageous embodiment of the present invention, the word lines which can be activated simultaneously by the control circuit are disposed in different memory cell arrays which are each assigned a word line or row line decoder.
In a further preferred embodiment of the present invention, the control circuit, for the simultaneous activation of exactly two word lines, is connected to word line decoders assigned to the respective memory cell arrays.
By way of example, if the integrated memory described conventionally has a burst length of two, then activation of exactly two word lines simultaneously results in a burst length of four, the correspondingly selected data being able to be combined by the multiplexer to form a continuous data stream.
In a further preferred embodiment of the present invention, the control circuit, for the simultaneous activation of exactly four word lines, is connected to word line decoders assigned to the respective memory cell arrays. In accordance with the above description for two word lines, given a conventional burst length of two, activation of four word lines simultaneously results in a burst length of eight.
In accordance with a concomitant feature of the invention, the multiplexer is constructed such that the predetermined burst length is dependent on a number of the word lines respectively activated simultaneously by the control circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having a plurality of memory cell arrays, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.